1. Field of the Invention
The present invention relates to a method of producing a semiconductor device, such as IC and LSI, and more particularly, to a method of forming the wiring of the semiconductor device, including a step of filling contact holes formed in a multilayer insulating layer with a metal selectively vapor-grown.
2. Description of the Related Art
During the production of a semiconductor device, to prevent the occurrence of step coverage problems (breakdown and thinning of a conductor line at a step) and to provide a flat surface level, a contact hole only is filled with a metal (e.g., a metal is selectively grown (deposited) within the contact hole).
A formation of the wiring of a semiconductor, using a metal selective growth process, is carried out, for example, as described below, with reference to FIGS. 1A and 1B.
As shown in FIG. 1A, a multilayer (quadruple-layer) insulating layer 2 is formed on a semiconductor substrate 1 of silicon (Si) by a conventional process. For example, the silicon substrate 1 is thermally oxidized to form a first insulating layer 2a of SiO.sub.2 on the surface thereof, and a second insulating layer 2b is formed on the layer 2a by depositing PSG (phosphosilicate glass) by a CVD (chemical vapor deposition) process. An SOG (spin on glass) is coated over the layer 2b to form a third insulating layer 2c, and then PSG is deposited on the layer 2c by a CVD process to form a fourth insulating layer 2d.
Since the production of a semiconductor device involves a repetition of the layer formation step and selective etching step, the surface of the device becomes uneven. Accordingly, a flattening technique, such as a coating with SOG is used, but since SOG generates undesirable H.sub.2 O gas during a heat-treatment (e.g., a heating of the substrate for depositing a CVD layer) and during usage of the device, the SOG coating is covered with an insulating layer of PSG and the like.
Next, a resist (polymeric material) is deposited on the fourth insulating layer 2d to form a resist layer, and this layer is then exposed and developed to form a resist mask (not shown). When the resist mask serves as a mask against an etchant, the insulating layers 2d, 2c, 2b and 2a are selectively etched by a RIE (reactive ion etching) method to open a contact hole 3 in the multilayer insulating layer 2, which hole 3 exposes a contact region of the substrate 1.
After removal of the resist mask, as shown in FIG. 1B, tungsten (W) is deposited (grown) within the contact hole 3 by a selective vapor-growth method, to form a metal layer (plug) 4. The metal layer 4 comes into contact with the substrate 1 and fills the contact hole 3 to reduce the height of a step at the hole edge and thereby form a smooth (flat) surface. Then, a predetermined conductor line layer (e.g., an aluminum line) 5 is formed on the metal layer 4 and the fourth insulating layer 2d, so that the line layer 5 is brought into electrical contact with the substrate 1 through the metal layer 4.
In addition to tungsten, the selectively vapor-growable metal can include aluminum (Al), copper (Cu), tantalum (Ta), and molybdenum (Mo), and a silicide of these metals.
Nevertheless, during the deposition of tungsten within the contact hole 3 only, to form the metal layer 4 by a metal selective vapor-growth method in the above-mentioned conventional process of forming the wiring of a semiconductor device, when the SOG insulating layer 2c of an insulating layer activating (promoting) a metal selective vapor-growth is exposed at the inside wall of the contact hole 3, the tungsten is abnormally deposited on a side wall portion of the SOG insulating layer 2c, and thus a growth of a tungsten portion 6 occurs as shown in FIG. 2. Therefore, in the worst case, the abnormally grown tungsten portion 6 blocks the contact hole 3 at the upper portion thereof, and accordingly a growing gas can not enter the contact hole 3 and the growing (depositing) of the metal layer 4 cannot proceed, with the result that a break in the wiring occurs. In other cases, the contact hole 3 is not completely filled with the metal layer 4, and thus a resistance of the metal layer 4 is increased.